The present disclosure relates to a voltage regulator, in particular to a low dropout voltage regulator.
The disclosure further relates to a corresponding system, a corresponding method and a corresponding design structure.
Voltage regulators are widely used in electronic circuits to supply the various components with the desired voltage level. Low dropout (LDO) voltage regulators are linear voltage regulators that are powered with a supply voltage that is close to the desired output voltage.
The stability of the LDO regulators is important for reliable device operation and is in particular challenging if the load of the LDO regulator comprises large changes and load steps.
Double data rate (DDR) memory links use burst-mode signaling, which means that data is transmitted in bursts of several bytes and in between these transmission bursts the transmitter is either in termination mode for the reception of data from the DRAM or in idle mode, the latter providing a high impedance state. The LDO regulator of such memory links has therefore to cope with large load steps when the DDR transmitters switch between active mode, termination mode or idle state. Large load steps are challenging for the loop dynamics of the voltage regulation because they strongly affect the frequency compensation and stability of the regulator.